In terms of our introduction to POPs, little of Chapter Six,
Interruptions, is of interest.
That is not to say it's not important material; indeed, it is.
However, for the beginning assembly programmer, undertaking
an indepth review of the material would be overwhelming.
Thus, we provide only a high level overview of interrupts.
Here are the main sections of this chapter:
Priority of Interruptions
The interruption mechanism permits the CPU to change its state as a
result of conditions external to the configuration, within the
configuration, or within the CPU itself.
To permit fast response to conditions of high priority and
immediate recognition of the type of condition, interruption
conditions are grouped into six classes:
external, input/output, machine check, program, restart, and
In essence, an interrupt stores the CPU's PSW and loads
a new PSW.
Both the Old PSW and New PSW locations are determined by
the interrupt class, and all of these locations occur within
the first page of low storage for the CPU.
Chapter Three, Storage, provided the exact details of where
these PSWs are stored and from where they are retrieved
in the Assigned Storage Locations section.
The Interruption Action subsection very clearly defines
what an interrupt causes to happen. It's a short section,
and I recommend you read it as best you can.
Consistent with the reference manual nature of POPs, there
is next an table showing what can be expected to occur
for each interrupt class. Glance over this table, particularly
noting the Old PSW and New PSW locations and PSW Mask Bits
for an EC mode PSW.
As we mentioned in the Control chapter, the PSW contains
mask bits which allow certain interrupt classes to be enabled or
disabled; meaning the interruption will be recognized or
queued for later recognition.
Within most interrupt classes, there is an interrupt code
that is stored (again at an interrupt class-specific location)
which provides further details about the interrupt.
Each interrupt can be divided into one of six classes, as
the first paragraph of the chapter described.
If you'll glance at the EC mode PSW, you might notice that
there are PSW mask bits for all but two interrupt classes:
restart, and supervisor call.
The reason for this is somewhat interesting.
The restart interrupt is used by the system operator to
invoke the operating system's restart routine (such as might
be desired when a user program is looping and won't cancel),
or by another CPU for internal system purposes.
At no time would you ever want to disable such behaviour, so
no "disable restart" mask bit is provided.
The reason why there's no "supervisor call disable" mask bit
is somewhat more subtle.
Essentially, the way to prevent supervisor calls is to not
issue the SVC instruction, since that's the only way to
generate a supervisor call interrupt.
In some ways, the omission of a supervisor call mask bit
is the essence of engineering, which I recently heard
described as: doing for 10 cents what any fool can do for a dollar.
A good friend also has an applicable definition: making things
you want from things you can get.
Having worked with the S/370 architecture for some time, I can
assure you it is well engineered.
The first time I sat down to read the POPs interruption chapter,
I headed straight for this section. It proved to provide a
mnemonic aid I still recall today: RIEMPS. That is the
sequence in which interrupt classes are recognized, in ascending
order. Ordinarily, it doesn't have much value to know this order
unless you're coding the Hercules emulator, but it does serve to
remind me of the various classes: restart, I/O, external, machine
check (repressible interrupts only), program, and supervisor call.
From the (repressible interrupts only) notation, you might intuit
that some machine checks are irrepressible.
Feel free to review whatever portions of this chapter strike your
fancy. If you plan on writing programs that might ever "blow up",
you should find at least a little bit of the Program Interruption
section of interest, but don't get bogged down in minutiae.