Understanding IEFBR14


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We now return to our IEFBR14 program. We will look at what POPs has to say about each of the two instructions in the program.



Subtract Logical


The first thing we need to do is find the SLR instruction in POPs. The POPs index quickly points us to the correct page, so let's go there.

Each S/370 instruction described in POPs tends to follow the same format:

Instruction diagram
Operation description
Resulting Condition Code
Program Exceptions
Programming Notes

There is a very brief description of this layout in Chapter 7 in the Instructions section, and most of the applicable notation such as R1 was introduced in Chapter 5, Program Execution.

Aside from those definitions, the reader is largely left to their own devices to figure out how this works. In fact, I don't even believe POPs ever formally names the instruction diagram; it's just what we'll call it. Likewise, we'll name the unlabeled section describing how an instruction operates the Operation Description.

Instruction Diagram

SLR  R1,R2         [RR]

X'1F'


R1


R2

0       7
8      11
12     15

First, note that POPs shows two Subtract Logical instructions. We only show the applicable format above, matching the instruction (Subtract Logical Register) in our program.

The instruction length for SLR is thus 16 bits, or two bytes. You might also notice that the SL instruction occupies 32 bits, or four bytes. The difference between the two instructions is that SLR provides a second operand in a GPR, while SL provides a second operand in a storage location. Generally the RR instructions mnemonics end with the letter R, although there are exceptions.

Observe the general format POPs uses here: first the instruction name, then for each of the instruction(s) the assembler instruction format followed by the machine code format. Take note that the subscript indicates the operand number, even when dealing with operands comprised of multiple fields such as X2,B2,D2.

As usual, we number the bits occupied by the instruction using standard S/370 notation along the bottom of the diagram.

Referring to the numbered bits above, we see the operand X'1F' occupies eight bits (one byte), and that each register operand (R1 and R2) occupies a nibble (four bits) each.

Operation Description

The second operand is subtracted from the first operand, and the difference is placed at the first-operand location. The operands and the difference are treated as 32-bit unsigned binary integers.

Referring back to the Instruction Diagram for SLR, note the subscripts on the operands which refer to the operand numbers matching what we just read in the Operation Description.

Since POPs didn't say otherwise, we can assume the registers being used are the General Purpose Registers.

The four R1 bits in the SLR instruction represent the GPR number of the first operand.

The four R2 bits in the SLR instruction represent the GPR number of the second operand.

At the completion of our program's SLR 15,15 instruction, the contents of GPR 15 (second operand) have been subtracted from GPR 15 (first operand) and stored in GPR 15 (first-operand location).

The effect of executing this instruction is to clear GPR 15 to binary zero.

Resulting Condition Code

This section shows the possible values the two condition code bits in the CPU's PSW can contain following the instruction's execution. With two bits for the condition code provided in the PSW, only four values (zero, one, two, and three) can be represented. The condition code is usually used to indicate the result achieved following the instruction's execution.

Value zero is never set by the Subtract Logical instruction, and this is indicated by the two dashes.

For the remaining condition code values, the result (zero or not zero) is indicated, as well as whether or not there was a carry. For the specific details on the meaning of carry, we need to read the Programming Notes section.

Following the execution of our program's SLR 15,15 instruction, we would expect the condition code would be two (Result zero; carry).

Program Exceptions

This section lists the possible exceptions the CPU can recognize for the instruction. Referring to the POPs Index, we note a long list of exceptions in addition to the primary reference listed following the word "exceptions". Chapter 6, Interruptions has a "Program Interruption" section that gives some interesting details, some of which we glossed over when we surveyed POPs.

Now would be a good time to read as much of the Program Interruption section there as you can digest (for beginning assembler programmers, that won't be much). About a dozen pages into the Program Interruption section, you'll finally encounter a subsection titled "Collective Program-Interruption Names" that discusses Access Exceptions. The key section of text is as follows:

Program interruptions are used to report exceptions and events which occur during execution of the program.

A program interruption causes the old PSW to be stored at real location 40 and a new PSW to be fetched from real location 104.

In the case of the Subtract Logical instruction, the only exception the CPU can recognize is an "access" exception, and only for the SL (not the SLR) instruction. So in the case of the SLR instruction, a program exception will never be produced.

Programming Notes

This section is where the authors of POPs typically provide some additional information necessary for understanding how the given instruction operates. In the case of Subtract Logical, this section contains further details on what "carry" means.



The BR instruction

Instruction Diagram

BCR  M1,R2         [RR]

X'07'


M1


R2

0       7
8      11
12     15

Recall that when we were searching the REFSUM for information on the BR instruction in our assembler program source, we found BC and BCR in the Extended Mnemonics section.

Since that time, we now have an online copy of the

GC33-4010-5 OS/VS-DOS/VSE-VM/370 Assembler Language
manual which describes Extended Mnemonics (page 72 in the PDF).

Referring to the numbered bits above, we see the operand X'07' occupies eight bits, and that the mask operand M1 and the branch address operand R2 occupy a nibble each.

The instruction length for BCR is thus 16 bits, or two bytes. You might also notice that the BC instruction occupies 32 bits, or four bytes. The difference between the two instructions is that BCR provides the branch address (the second operand) in a GPR, while BC provides a storage location given by adding a "base" register, an "index" register, and a displacement all specified by the second operand.

Operation Description

The instruction address in the current PSW is replaced by the branch address if the condition code has one of the values specified by M1; otherwise, normal instruction sequencing proceeds with the updated instruction address.

Since POPs didn't say otherwise, we can assume the registers being used are the General Purpose Registers.

The actual contents of the four M1 bits represent the mask, which will be the first operand.

The actual contents of the four R2 bits represent the GPR number, which will contain the branch address (the second operand) in bits 8-31 (24 bit addressing).

Thus, at the completion of our program's BCR 15,14 instruction, the contents of GPR 14 (second operand) have replaced the 24 bit "next" instruction address in the PSW.

We know that will be the case because the mask value 15 equals B'1111', which matches all four possible condition code values. So regardless of the condition code, the mask evaluates true. When the mask evaluates true, the branch is sometimes said to be "taken".

The effect of executing this instruction is to return to whatever part of MVS called our IEFBR14 program.

Condition Code

The code remains unchanged.

Since the condition code remains unchanged, we would expect that the REFSUM entry for BCR does not have the (c) notation.

Program Exceptions

None.

Anyone with programming experience in MVS might be surprised to see POPs say that there are no program exceptions from the BCR and BC instructions. Many of you might have "branched to location zero" when you called a program that was left unresolved at the end of a linkedit.

What POPs means here is that the BCR and BC instructions themselves won't cause program exceptions. However, when your program sets the "next instruction" address in the PSW to zero, you can generally count on a program exception when the CPU attempts to execute the instruction contained at location zero. The distinction is that the program exception is related to what is contained at location zero, rather than the BCR or BC instruction itself.

However, counting on the contents of location zero to "blow up" your program is a bad idea. Until we learn about the MVS ABEND service, executing a halfword of X'0000' is a more reliable approach since the S/370 architecture guarantees X'0000' is not a valid instruction.

Programming Notes

As promised, POPs mentions the instruction sample in Appendix A, so if you're still confused about how it works at the end of this section then examining the sample might be a good idea.



Reviewing IEFBR14

Our IEFBR14 program executed two instructions:


         SLR   15,15           set return code zero
         BR    14              return to MVS

From the fact that MVS indicated the IEFBR14 step in our JCL completed with return code zero, we can deduce that GPR 15 contains the return code from our program when it completes, and that GPR 14 contains the return address back to the part of MVS that called our program.

The standard definition of these two GPRs is part of something called "standard linkage conventions", which we will discuss shortly.


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